1. Field of the Invention
The present invention relates to non-volatile memory, and more particularly, non-volatile memory having a row driving circuit with shared level shift circuits.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a block diagram of prior art flash memory 10. The flash memory 10 comprises a first decoding circuit 12, a second decoding circuit 14, a row driving circuit 16, a power supply circuit 18 and a plurality of memory blocks 20a, 20b each comprising a plurality of memory units 24. The row driving circuit 16 comprises a plurality of word line driving circuits 22a, 22b each for driving a plurality of word lines WL0˜WLn. Each of the word lines WL0˜WLn is connected to a plurality of memory units 24. The first decoding circuit 12 is used to decode a memory address Add of the flash memory 10 so as to generate a first decoding signal XP for selecting one of the word line driving circuit 22a, 22b. If the word line driving circuit 22a is selected, the word line driving circuit 22a will be used to access the memory block 20a because the memory block 20a is connected to the word line driving circuit 22a. The second decoding circuit 14 is used to decode the memory address Add so as to generate a second decoding signal XT for selecting one of the word lines WL0˜WLn. The power supply circuit 18 provides power to the row driving circuit 16 so as to access data to and from the memory blocks 20a, 20b. 
Please refer to FIG. 2. FIG. 2 is a circuit diagram of the word line driving circuit 22a. The word line driving circuit 22a comprises a NAND gate 26 and a plurality of NOR gates 28a˜28c. The first decoding signal XP is used to select one of the word line driving circuits 22a, 22b of the row driving circuit 16. If the row driving circuit 16 has eight word line driving circuits, then three first decoding signals XPA, XPB, XPC are input to the NAND gate 26 of each word line driving circuit 22a, 22b to enable one of the eight word line driving circuits. Further each of the word line driving circuit 22a, 22b comprises eight NOR gates each corresponding to a word line. For example, the NOR gate 28a is corresponding to a word line WL0, the NOR gate 28b is corresponding to a word line WL1, and the NOR gate 28c is corresponding to a word line WL7. Because the word line driving circuit 22a is connected to eight word lines WL0˜WL7, the second decoding signal XT comprises eight decoding signals XT0˜XT7 for selecting one of the word lines WL0˜WL7 accordingly.
Between each of the NOR gates and its corresponding word line WL0˜WL7 is connected a level shift circuit. For instance, the NOR gate 28a is connected to a level shift circuit 30a, the NOR gate 28b is connected to a level shift circuit 30b, and the NOR gate 28c is connected to a level shift circuit 30c. The level shift circuits 30a, 30b, 30c have identical circuit structure. Each of the level shift circuits 30a, 30b, 30c comprises two P-type transistors 32a, 32c, two N-type transistors 32b, 32d, and an inverter 34. When the flash memory 10 accesses data, the power supply circuit 18 will output 3.3V for V1 and 0V for V2 respectively. Thus when the output end of the NOR gate 28a has a logic value of 1, the transistor 32b will be turned on so that a node P1 will have a voltage close to 0V (logic 0), and the transistor 32c will be turned on so that a node P2 will have a voltage close to 3.3V (logic 1) while the transistors 32a, 32d are closed. Thus the word line WL0 will output a voltage of 3.3V.
In the prior art, each of the word line WL0˜WL7 is connected to a corresponding level shift circuit. And each of the level shift circuits is composed of at least six transistors. However the flash memory 10 generally has many word lines, thus a massive number of transistors need to be disposed on the row driving circuit 16, making the chip of the flash memory 10 oversized.